Senior ASIC Verification Engineer - UVM & SystemVerilog
Role Description & Technical Scope
European Tech Recruit is partnering with a leading technology innovator in Cork, Ireland, to hire an experienced Verification Engineer. You will apply UVM, formal verification, and constrained‑random techniques to verify ASICs and ensure tapeout‑quality sensor algorithms.
Responsibilities include building RTL testbenches, C models, SystemVerilog assertions, Python automation, and regression frameworks. You will collaborate across design, systems and software teams and contribute to documentation
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Key Details
- Date Posted: 19 Oct 2026
- Location: cork
- Employment: Permanent
- Workplace: Hybrid
- Domain: Quality Engineering
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European Tech Recruit
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