Senior SoC Verification Engineer – SystemVerilog/UVM
Role Description & Technical Scope
ST assume una posizione di Senior Digital Verification Engineer – SoC a Napoli. Il candidato lavorerà su testbench SystemVerilog UVM, sviluppando test in C e script Python per automazione, analisi e coverage.
Collaborerà con team RTL, architettura e firmware per definire strategie di verifica e garantire qualità elevata in ambienti automobilistici/industriali. Viene richiesto un background in ingegneria elettronica o informatica, 5–8 anni di esperienza, conoscenza di tool EDA e ambienti
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Key Details
- Date Posted: 23 Oct 2026
- Location: napoli
- Employment: Permanent
- Workplace: Hybrid
- Domain: General
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